The design of the pMOSFET presents the most vexing obstacles to sub-100nm gate length CMOS technologies. In particular, boron penetration from the gate electrode through the gate oxide into the channel, and enhanced diffusion of boron from the source and drain regions due to defects introduced during ion implantation threaten pMOS viability. This figure shows a scanning capacitance micrograph of the two-dimensional doping profile observed in an 80nm gate length pMOSFET. Red or pink coloring indicates the p-type doping, while the n-type doping is indicated by blue. The vertical (55nm) and lateral (30nm) extent of the lightly doped drain and source regions under the polysilicon gate, as well as the heavily doped drain, source (80nm) and gate electrodes are apparent. The 20nm channel is clearly indicated in the micrograph and provides us with incontrovertible evidence that a sub-100nm pMOS technology utilizing hyper-thin gate oxides and ultra-shallow junctions is viable provided that the thermal budget is less than 1000C for 10 seconds and ultra-low energy implants (<1keV) are used.
 

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